Field of the Invention
The present invention generally relates to Integrated Circuit (IC) manufacture and more particularly to manufacturing integrated circuits with metal gate Field Effect Transistors (FETs) with abrupt junctions.
Background Description
Primary integrated circuit (IC) chip manufacturing goals include increasing chip density and performance at minimized power consumption, i.e., packing more function operating at higher speeds in the same or smaller space. Transistors or devices are formed by stacking layers of shapes on the IC, e.g., printed layer by layer on a wafer using photolithographic techniques. A simple field effect transistor (FET), or device, is defined by the intersection of two shapes, one for channel and one for gate. Generally, device current is governed by the ratio of its width to length. Shrinking/reducing chip feature sizes to increase density and performance provides a corresponding reduction in minimum device dimensions, e.g., minimum channel length. Using shorter devices allows/requires thinner vertical feature dimensions, e.g., a shallower channel layer and junction depth, thinner gate dielectric, and connecting wires and vias.
Most state of the art ICs are made on a bulk wafer or in silicon on insulator (SOI) wafer, in the well-known complementary insulated gate field effect transistor (FET) technology known as CMOS for minimized power consumption. A typical CMOS circuit includes paired complementary devices, or FETs, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually both gated by the same signal. Since the pair of devices in an ideal inverter have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (modeled simply as a closed switch), the other device (the PFET) is off, not conducting (modeled as an open switch) and, vice versa. With one switch closed and the other open, ideally, there is no static current flow.
No device is ideal, however, and there are unwanted currents flowing even in off devices. Further, as device dimensions shrink, previously negligible device characteristics have become appreciable. For example, gate to channel, gate to source/drain, subthreshold current, and other short channel effects may be problematic in state of the art short channel FETs. Especially for complex chips and arrays with a large number of devices, these short channel effects can be overwhelming. When multiplied by the millions and even billions of devices on a state of the art IC, even 100 picoAmps (100 pA) of leakage in each of a million circuits, for example, results in chip leakage on the order of 100 milliAmps (100 mA).
Replacing FET gate oxide with a high-k dielectric has eliminated most of the unwanted gate oxide leakage, e.g., gate to channel and/or gate to source/drain. Since, polysilicon cannot be used with high-k dielectrics, work function metal and aluminum is being used for gates instead of polysilicon. In what is known as Replacement Metal Gate (RMG) FETs, typical polysilicon gate FETs are formed through source/drain extension, source/drain diffusion and interlayer dielectric (ILD) formation on the source/drain diffusions. Then, the polysilicon gates are removed and replaced, e.g., when contacts are formed through the ILD.
Unfortunately, forming well-controlled abrupt junctions using state of the art RMG manufacturing processes has been challenging. These processes typically involve various annealing temperatures post extension and source/drain junction formation. These various annealing temperatures affect junction position, e.g., causing unwanted out-diffusion. Diffusing FET junctions may tend to migrate towards each other enhancing short-channel effects. Moreover, high-mobility channel materials, such as germanium (Ge) or III-V semiconductor, have well known material instability issues with very high temperature dopant drive-in, or activation. Source/drain junctions in these materials become very resistive as a result of the low temperature processing required to form a high-k/metal gate (HK/MG) stack, i.e., to replace polysilicon gates with metal gates.
Thus, there is a need for reducing short channel effects for RMGFETs; and more particularly, for forming abrupt junctions that are unaffected by subsequent RMGFET formation steps.